The present invention relates to semiconductor devices, and more specifically, to the formation of metallic gate electrodes using a replacement gate process technique.
Advances in specific semiconductor disciplines, such as photolithography, and dry etching, have been major contributors to micro-miniaturization, however structural innovations, such as the use of self-aligned contact, (SAC), openings, and SAC structures, have also played a vital role in achieving the performance and cost objectives of the semiconductor industry.
In advanced sub-32 nanometer (nm) technologies, a replacement metal gate (RMG) can be employed with a pre/post metal anneal (PMA). However, an issue is the tight gate-to-gate spacing and a design requirement to place a contact there between. In many cases, the gate-to-gate pitch is so narrow that placing a contact between two gates using direct patterning is challenging because, for example, of the small contact size. In some cases, design requirements can result in applying up to six to eight masks during manufacture to overcome such constraints, however, the overlay between gate and contact remains problematic.
Methods for 10 nm MOL (middle of the line) technologies use SAC processes with three masks, CA/CC/CE, in a triple exposure process, litho-etch-litho-etch-litho-etch (LELELE). However, such processes can be difficult for manufacture. For example, because each litho and etch differs and is dependent on pattern density leading, etch variability is present. Processes are susceptible to SAC underetching and overetching, which could result in either high contact resistance and a resultant increase in leakage (in the case of overetching or gouging of epitaxial layers), or electrical opens (in the case of underetching). Furthermore, using multiple patterning technologies, such as LELELE processes, can prevent the use of fully landed self aligned contacts and increase the potential for misalignment. In addition, in such processes, a SAC cap formed by the replacement metal gate recess/insulator fill and polish process can have high variation and tolerances. Moreover, the need for a SAC cap in such processes increase the required thickness of gate poly which results in difficulties in polysilicon conductor (PC) etch. In addition, such devices can be susceptible to hollow metal void defects. Thus, improved processes for RMG technologies are needed.